Monolog For Bassoon By Isang Yun Music Essay

Monolog For Bassoon By Isang Yun Music Essay Isang Yun was a composer with Korean ethnicity who is well known in the music world especially in Europe as he spent a major portion of his life in Germany and died there too. In his initial years of composing, his compositions were not well known in Korea due to the political issues surrounding the East Berlin Event. Inferring from his biography, it seemed that he wished to see Korea as a unified nation. Between the period of 1956 to 1995, Isang Yun composed music in Germany and other European countries. He also composed vast amount of pieces and his works were written in almost every genre, such as instrumental sonatas, operas, symphonies, and cantatas. While his works have been largely performed and studied in Europe, Japan, and even North Korea, South Korean officials have thoroughly prohibited his music and consider the composer dangerous politically. Isang Yun often visited North Korea without permission from the South as North Korea supported scholarships and living expenses for him. However, after a change of regime in 1982, the national symphony orchestra of South Korea first introduced his works in South Korea. From this time, Yuns music began to be studied by musicians in the South. This paper will discuss in musical theoretical detail one of his works, Monolog for bassoon His well composed work, Monolog for Bassoon was composed in 1983, this was the mid period of Yuns well accomplished compositional career. During this stage of his life, he had already achieved mastery over the formal techniques of the European avant-garde and had moved more into composing within a more free atonal style. The Monolog for bassoon is quintessential of Yuns typical mature style wherein he fusions the use of free atonality with elements from his ethnic Korean lineage. The Monolog for bassoon, which has so far been recorded by at least five prominent bassoonists, is a concrete testament to Yuns growing prominence as a 20th century composer. It shows Yuns unique compositional angle which uniquely combines ethnic Korean inspirations in a work for bassoon, which is a distinctly Western instrument. The Monolog for bassoon also warrants a close study, as it is his only solo work for bassoon, and is an emerging standard of 20th century avant-garde bassoon repertoire. During his initial years into composing, Yun was fond of and got acquainted with European music and constantly found different sought out ways to learn more about European music history, style, and compositional methods. Because of his inclination towards western music more so European music, he also developed inspiration in the musical traditions of his home country, Korea. It was only after his journey to Europe that Yun began to foster and incorporate traditional Korean elements into his music. Yun himself admitted this truth through the following quote: When I was in Korea, I enjoyed and listened to our rich Korean musical traditions for entertainment. But I realized the hidden treasures of Korean traditional music for the first time only after I came to Europe. Keith Howard notes that prior to Yuns journey to Europe, his works show no attempt to incorporate elements from Korean traditional music. Yun later removed all works from circulation that he had written prior to his study in Europe as he felt they were not representative of his mature compositional voice. Whilst presenting into radio broadcasts in Freiburg in 1960 on the subject of traditional East Asian music, he began to develop his distinct and unique composing style. Yun also spent a major part of his time to study traditional East Asian music so he could play them in his broadcasts. Due to this research Yun was inspired to compose Loyang, a beautifully composed work that incorporated the mood of ancient court music, the sounds of traditional Korean instruments, as well as the principles of Taoism. But Yuns method of incorporating these elements was not literal in the least. Jeongmee Kim explains: He was not interested in quoting folk tunes, nor borrowing traditional Asian instruments, nor composing nostalgic song lyrics. Yuns Korean musical heritage is expressed through more abstract, philosophical, and internalized use of ethnic materials, in particular Hauptton/Hauptklang technique. He relied on the use of Korean classical musical forms and Asian philosophy to compete with the equivalent in Europe. These shape and propel the sounds and structure of his works, while the Western musical heritage and its instruments provide the physical means to articulate Yuns complex sound world. Quite centric to Yuns music can be found a Korean view of sound. While Western ears are accustomed to hearing a melodic figure accompanied by harmonic progression, Eastern music relies heavily on the role of an individual or central tone. The tone itself is celebrated; adorned with a huge variety of ornaments. These ornaments are not intended to encompass the central tone within a melody, rather they are an essential part of how the tone is able to express itself. The concept of the central tone is prevalent in many Asian countries and spans various genres of Asian music. Yun describes this phenomenon in a speech he gave at a conference in Berlin: While in European music the concept of form plays a decisive part, and notes become significant only when a whole group of them are related horizontally as melody or vertically as harmony, the thousand-year-old tradition of Eastern Asiatic music places the single note, the constructive element, in the foreground. In European music only a series of notes comes to life, so that the individual tone can be relatively abstract, but with us the single tone is alive in its own right. Our notes can be compared to brush strokes as opposed to pencil lines. From beginning to end each note is subject to transformations; it is decked out with embellishments, grace notes, fluctuations, glissandi, and dynamic changes; above all, the natural vibration of each note is consciously employed by a means of expression. A notes changes in pitch are regarded less as intervals forming a melody than as an ornamental function and part of the range of expression of one and the same note. This method of treating individual notes sets my music apart from other contemporary works. It gives it an unmistakably Asiatic color, which is evident even to the untrained listener. Keith Howard discusses some meaningful reasons which explain the reason for Korean music being structured in that way. The initial part is the ironic yet well complementing relationship between yin and yang. After which is the concept of never-ending movement. Nature is held in high regard in the east asian culture more so with the continuous flow of elements like water, air etc. Now from an abstract or musical view, the flow of sound is thought to be continuous as well. Music exists before sound begins, and continues after sound ends. This is one of the reasons why Yun compares the single tone to brush strokes as opposed to pencil lines. A pencil line has a definite beginning and ending, as well as a uniform shape and consistency throughout. But in a brush stroke it is hard to determine where the actual beginning and ending occur. Although to the naked eyes it may show as a single line, it can show different views in a myriad of ways and also have contrasting qualities within each u nique stroke, which more precisely mimics the flow of nature. He goes on more to explain his view of continuous flow in an interview with Bruce Duffie where he quotes: My music doesnt have a beginning or an end. You could combine elements from one piece into another piece very wellà ¢Ã¢â€š ¬Ã‚ ¦. Music flows in the cosmos and I have an antenna which is able to cut out a piece of the stream. The part which Ive cut out is organized and formed through my own thought and body processes, and I commit it to paper. Thats why my music is always continuous like the clouds that are always the same but are never alike one to another. Howard also suggests that the physical structure and musical capabilities of traditional Korean instruments have had a profound impact on the Korean concept of tone. While each instrument is unique in tone and structure, they all are extremely flexible in terms of pitch. Many instruments are so flexible that it can be difficult to produce a steady tone. This is directly linked to the Korean musical ideal of sound being embellished and ever changing. As Yun mainly did composing in the sphere of Western art music, wherein a comprehensive understanding of Korean ornamentation is not mandatory, he does not leave the art of ornamentation up to the performer. He makes it a point to word minute details of the ornamentation, few of which exist within the framework of Western notation, others of which he must create new symbols and explanations for, as they are not part of the conventional vocabulary for Western musicians. This was a challenging process for Yun because in his thoughts he held a meticulously detailed vision of what the ornamentation should sound like. On this part he was quoted as, I wrote down the playing techniques for instrumentalists as they are used in Korea on the old instruments, thus as a very accurate vibrato and many sorts of glissando. In Korea there are of course about thirty kinds of glissando. To truly emulate the sounds of traditional Korean instruments, Yun had to create new, and often very difficult, tech niques for the performers. Isang Yuns Monolog for bassoon was mainly composed between the years 1983 to 1984, however the actual roots of this work had begun some years prior along with his other work Clarinet Concerto. The Clarinet Concerto was composed by Yun in the year 1981 especially for Swiss clarinetist Eduard Brunner, who was the principal clarinetist of Munichs Bavarian Radio Symphony Orchestra for about 30 years. He premiered the work in Munich on January 29, 1982. Certain points which were notable about the Clarinet Concerto is the usage of bass clarinet instead of clarinet because of the solo voice during the middle movement. In the following year, Yun removed the solo line from the second movement and then used it as the structural basis for a solo bass clarinet work. The resulting composition of this which was written for Dutch bass clarinet virtuoso Harry Sparnaay, became Yuns Monolog for bass clarinet and was then premiered on April 9, 1983. Expecting some changes and more likely to accommodate range, Yun also published a version of the same work for bassoon. Yun was quoted in an interview with Bruce Duffie in 1987 that he composed strictly by commission, and his scores typically included a dedication to the commissioner. However, the Monolog for bassoon contains no such dedication and it is unknown whether it was created for a particular individual. It was premiered on February 3, 1985 by French bassoonist Alexandre Ouzounoff. Precedent for Yuns solo works being performed on other instruments had been set several years prior with Piri, a composition for solo oboe. Piri was composed in 1971 for oboist Georg Meerwin, which immediately gained quick popularity. Before long, musicians of other instruments took notice of Piri and began to perform it. Clarinetists specifically performed and recorded Piri, which also including Eduard Brunner. Wolfgang Sparrer was quoted on his observation about about Piri as: Although it was originally written for oboe, the composer has allowed interpretations for other instruments. Due to its high demands regarding playing technique and successful balance between construction and expression, Piri achieved so much popularity within only a few years that it was often chosen as a compulsory piece in music competitions. Due to this well spread acceptance and versatility of Piri, Yun may have anticipated the idea of creating an alternate edition of Monolog for bass clarinet for bassoon. Since there are distinct differences in range, key, and clef notation between the two instruments, publishing a new version of the work for bassoon was necessary to encourage performances. As this analysis specifically addresses the Monolog for bassoon, an in-depth discussion of Yuns Monolog for bass clarinet will not be included with the exception of highlighting the differences between the bassoon and bass clarinet versions as explained below. In a discussion of his compositional process, Yun was quoted by Luise Rinser: I do not exhaust my possibilities in any one piece. There always remains something unsolved in form. I make that the starting point of another work. I must always take something new as a challenge. If someday no more new ideas come up, I would stop composing. This statement not just shows the well synergized and critical parts in Yuns works, but also provides an answer for his use of the middle movement of the Clarinet Concerto as the basis for an expanded work that would eventually become the Monolog for bassoon. The Monolog for bassoon well showcases Yuns unique compositional fusion of Eastern and Western elements. Although this work at an initial look seems like a general late twentieth century avant-garde work for bassoon utilizing extended techniques within a non-tonal compositional context, Yuns compositional approach looks to specifically convey traditional Korean philosophies, sound ideals, and instrumental techniques. Understanding his compositional method is a key to the performers comprehension of the work. If only viewed with a Western outlook analysis of this work, there is a possibility to overlook critical elements in the work like main tone versus ornament, or treatment of the ornaments themselves, while making other analytical associations which he did not intend, such as relying on motivic development and harmonic motion to propel the music rather than melodic growth. Just with all musical genres, it is more feasible to have a comprehensive understanding of the main composers musical perspective. This understanding also holds true for music of the twentieth-century than it is for earlier periods, particularly as modern musical influences become more and more diverse and reach beyond the bounds of traditional Western classical music. Bibliography / Discography Hur, Dae-Sik. A Combination of Asian Language with Foundations of Western Music: An Analysis of Isang Yuns Salomo for Flute Solo or Alto Flute Solo. PhD diss., University of North Texas, 2005. Kim, Jeongmee. Musical Syncretism in Isang Yuns Gasa. In Locating East Asia in Western Art Music, edited by Yayoi Uno Everett and Frederick Lau, 168-192. Middletown, Conn: Wesleyan University Press, 2004. Choi, Yulee. The Problem of Musical Style: Analysis of Selected Instrumental Music of the Korean-Born Composer Isang Yun. Ph.D. diss., New York University, 1992. Helicon, David Currnings, ed. Yun, Isang. Random House Encyclopedia Dictionary of Classical Music. Publishing Ltd., Oxford, 1997. 749. . . Yun, Isang. In Contemporary Composers. Edited by Brian Morton and Pamela Collins. New York: St James Press, 1992. Kim, Chul-Hwa. The Musical Ideology and Style of Isang Yun, As Reflected in His Concerto for Violoncello and Orchestra (1975/76). Ph.D. diss., University of Illinois at Urbana- Champaign, 1997. Kim, Doosook. A Recording and an Analytical Overview of Two Violin Works by Isang Yun. Ph.D. diss., Arizona State University, 1996. Kim, Jeongmee. The Diaporic Composer: The Fusion of Korean and German Musical Cultures in the work of Isang Yun. Ph.D. diss., University of California, 1999. Kim, Yongwan. Yun Isang Yun Ku. Seoul: Hankuk Yesul Jonghap Hakgou Press, 2001. Kunz, H. Yun, Isang. In The New Grove Dictionary of Music and Musicians Vol. 27. Edited by Stanley Sadie. London: Macmillan, Publishers, 2001. 696-697. Musique pour Basson et Piano Vol.2 Performer: Dag Jensen, Midori Kitagawa Composer: Paul Hindemith, Olav Berg, Othmar Schoeck, Otmar Nussio, Isang Yun, et al. Audio CD (March 23, 1999) Label: MDG Records

Input/Output Organization

INPUT/OUTPUT ORGANIZATION †¢ Accessing I/O Devices †¢ I/O interface †¢ Input/output mechanism Memory-mapped I/O y pp / Programmed I/O Interrupts Direct Memory Access †¢ Buses Synchronous Bus Asynchronous Bus I/O in CO and O/S †¢ †¢ †¢ Programmed I/O Interrupts DMA (Direct memory Access) A bus is a shared communication link, which uses one , set of wires to connect multiple subsystems. The two major advantages of the bus organization are versatility and low cost. Accessing I/O Devices Most modern computers use single bus arrangement for connecting I/O devices to CPU & Memory †¢ The bus enables all the devices connected to it to exchange information †¢ Bus consists of 3 set of lines : Address, Data, Control †¢ Processor places a particular address (unique for an I/O Dev. ) on address lines †¢ Device which recognizes this address responds to the commands issued on the Control lines †¢ Processor requests for either Read / Write †¢ The data will be placed on Data lines Hardware to connect I/O devices to b t bus Interface Circuit – Address Decoder – Control Circuits – Data registers – Status registers †¢ The Registers in I/O Interface – buffer and control †¢ Flags in Status Registers like SIN, SOUT Registers, SIN †¢ Data Registers, like Data-IN, Data-OUT I/O interface for an input device Memory Address Processor Data Control Address Add Decoders Control C t l circuits Data d t t D t and status registers I/O /O Interface Input device (s) p ( ) Input Output mechanism h i †¢ Memory mapped I/O †¢ Programmed I/O †¢ Interrupts †¢ DMA (Direct memory Access)A bus generally contains a set of control lines and a set of data lines. The control lines are used to signal requests and acknowledgments, and to indicate what type of information is on the data lines. The control lines are used to indicate what the bus contains and to implement the bus p rotocol. The data lines of the bus carry information between the source and the destination. This information may consist of data, complex commands, or addresses. Buses are traditionally classified as processor-memory di i ll l ifi d buses or I/O buses or special purposed buses (Graphics, etc. ).Processor memory buses are short, generally high speed, and matched to the memory system so as to maximize memoryprocessor bandwidth. I/O b buses, b contrast, can be lengthy, can have many by t t b l th h types of devices connected to them, and often have a wide range in the data bandwidth of the devices connected to them. I/O buses do not typically interface directly to the memory but use either a processor-memory or a backplane bus to connect to memory. The major disadvantage of a bus is that it creates a communication bottleneck possibly limiting the maximum I/O bottleneck, throughput.When I/O must pass through a single bus, the bus bandwidth of that bus limits the maximum I/O throughput. Reason why b R h bus d i design is so difficult : i diffi lt – the maximum bus speed is largely limited by physical factors: the length of the bus and the number of devices. These physical limits prevent us from running the bus arbitrarily fast. – In addition, the need to support a range of devices with widely varying latencies and data transfer rates also makes bus design challenging. – it becomes difficult to run many parallel wires at high speed due to clock skew and reflection reflection.The two basic schemes for communication on the bus are synchronous and asynchronous. If a bus is synchronous (e. g. Processor-memory), it includes a clock in the control lines and a fixed protocol for communicating that is relative to the clock. g This type of protocol can be implemented easily in a small finite state machine. Because the protocol is predetermined and involves little logic, the bus can run very fast and the interface logic will be small. Synchronous buses h ave two major disadvantages: – First, every device on the bus must run at the same clock rate. Second, because of clock skew problems, synchronous buses cannot be long if they are fast. An A asynchronous b h bus i not clocked. It can accommodate a is t l k d d t wide variety of devices, and the bus can be lengthened without worrying about clock skew or synchronization problems. To coordinate the transmission of data between sender and receiver, an asynchronous bus uses a handshaking protocol. Three special control lines required for hand-shaking: ReadReq: Used to indicate a read request for memory. The address is put on the data lines at the same time.DataRdy: Used t i di t th t th d t D t Rd U d to indicate that the data word is now ready on the di d th data lines; asserted by: Output/Memory and Input/I_O Device. Ack: Used to acknowledge the ReadReq or the DataRdy signal of the other party. I/O Dev. Memory Steps after the device signals a request by raising ReadReq and putti ng the address on the Data lines: 1. When memory sees the ReadReq line, it reads the address from the data bus and raises Ack to indicate it has been seen. 2. As the Ack line is high – I/O releases the ReadReq and data lines. g / q 3.Memory sees that ReadReq is low and drops the Ack line to acknowledge the ReadReq signal (Mem. Reading in progress now). 4. This step starts when the memory has the data ready. It places the data from the read request on the data lines and raises DataRdy. 5. The I/O device sees DataRdy, reads the data from the bus, and signals that it has the data by raising Ack. 6. On the Ack signal, M/M drops DataRdy, and releases the data lines. 7. Finally, the I/O device, seeing DataRdy go low, drops the Ack line, which indicates that the transmission is completed. Memory mapped I/O I/O devices and the memory share the same address space the space, arrangement is called Memory-mapped I/O. In Memory-mapped I/O portions of address space are assigned to I/O devi ces and reads and writes to those addresses are interpreted as commands to the I/O device. †¢ â€Å"DATAIN† is the address of the input buffer associated with the keyboard. – Move DATAIN, R0 reads the data from DATAIN and stores them into processor register R0; – Move R0, DATAOUT sends the contents of register R0 to location DATAOUT g Option of special I/O address space or incorporate as a part of memory address space (address bus is same always).When the processor places the address and data on the memory bus, the memory system ignores the operation because the address indicates a portion of the memory space used for I/O. The device controller, however, sees the operation, records the data, and transmits it to the device as a command. User programs are p p g prevented from issuing I/O g / operations directly because the OS does not provide access to the address space assigned to the I/O devices and thus the addresses are protected by the address translatio n. Memory mapped I/O can also be used to transmit data by writing or reading to select addresses.The device uses the address to determine the type of command, and the data may be provided by a write or obtained by a read. A program request usually requires several separate I/O operations. Furthermore, the processor may have to interrogate the status of the device between individual commands to determine whether the command completed successfully. DATAIN DATAOUT STATUS CONTROL 7 6 5 4 DIRQ KIRQ DEN KEN SOUT SIN 3 2 1 0 I/O operation involving keyboard and display devices Registers: DATAIN, DATAOUT, STATUS, CONTROL Flags: SIN, SOUT – Provides status information for keyboard nd display unit KIRQ, DIRQ – Keyboard, Display Interrupt request bits DEN, KEN –Keyboard, Display Enable bits Programmed I/O †¢ CPU has direct control over I/O – S Sensing status i t t – Read/write commands – Transferring data †¢ CPU waits for I/O module to comple te operation †¢ Wastes CPU time In this case, use dedicated I/O instructions in the processor. These I/O instructions can specify both the device number and the command word (or the location of the command word in memory). The processor communicates the device address via a set of wires normally included as part of the I/O bus.The actual command can be transmitted over the data lines in the bus. bus (example – Intel IA-32) IA-32). By making the I/O instructions illegal to execute when not in kernel or supervisor mode user programs can be mode, prevented from accessing the devices directly. The process of periodically checking status bits to see if it is time for the next I/O operation, is called polling. Polling is the simplest way for an I/O device to communicate with the processor processor. The I/O device simply puts the information in a Status register, register and the processor must come and get the information.The processor is totally in control and does all the w ork. A ISA program to read one line from the keyboard, store it in memory buffer and echo it back to the display buffer, The disadvantage of polling is that it can waste a lot of processor time because processors are so much faster than I/O devices devices. The processor may read the Status register many times, only to find that the device has not yet completed a comparatively slow I/O operation, or that the mouse has not budged since the last time it was polled.When the device completes an operation, we must still read the status to determine whether it (I/O) was successful. Overhead in a polling interface lead to the invention of interrupts to notify the processor when an I/O device requires attention from the processor. Interrupt-driven I/O, Interrupt driven I/O employs I/O interrupts to indicate to the processor that an I/O device needs attention. When a device wants to notify the processor that it has completed some operation or needs attention, it causes the processor to be in terrupted.Interrupts I/O INTERRUPT Processor †¢ When I/O Device is ready, it sends the INTERRUPT signal to processor via a dedicated controller line †¢ Using interrupt we are ideally eliminating WAIT period †¢ In response to the interrupt, the processor executes the Interrupt Service Routine (ISR) †¢ All the registers flags program counter values are saved registers, flags, by the processor before running ISR †¢ The time required to save status & restore contribute to execution overhead ? â€Å"Interrupt Latency† p y nterrupt-acknowledge signal – I/O device interface p y accomplishes this by execution of an instruction in the interrupt-service routine (ISR) that accesses a status or data register in the device interface; implicitly informs the device that its interrupt request has been recognized. IRQ signal is then removed by device. ISR is a sub-routine – may belong to a different user than the one being executed and then halted. The c ondition code flags and the contents of any registers used by both the interrupted program and the interrupt-service interrupt service routine are saved and restored restored.The concept of interrupts is used in operating systems and i many control applications, where processing of d in l li i h i f certain routines must be accurately timed relative to external events (e. g. real-time processing). Interrupt Hardware p Pull up Pull-up resister INTR = INTR1 +†¦.. +INTR n INTR An equivalent circuit for an open drain bus used to implement a open-drain common interrupt-request line Interrupt Hardware Supply pp y R INTR Processor Pull-up resister INTR 1 INTR 2 INTR 3 INTR = INTR1 +†¦.. +INTR n GND INTR Enabling and Disabling Interrupts Device activates interrupt signal line and waits with this signal activated until processors attends †¢ The interrupt signal line is active during execution of ISR and till the device caused interrupt is serviced †¢ Necessary to ensure t hat the active signal does not lead to successive interruptions (level-triggered input) causing (level triggered the system to fall in infinite loop. †¢ What if the same d i h h device i interrupts again, within an ISR ? i i hi †¢ Three methods of Controlling Interrupts (single device) – Ignoring interrupt – Disabling interrupts – Special Interrupt request line Ignoring Interrupts – Processor hardware ignores the interrupt request line until the execution of the first instruction of the ISR completed – Using an interrupt disable instruction after the first instruction of the ISR – no further interrupts – A return from interrupt instruction is completed before further interruptions can occur †¢ Disabling Interrupts – Processor automatically disables interrupts before starting the execution of the ISR – The processor saves the contents of PC and PS (status register) before performing interrupt disabling. The interrupt-enable is set to 0 – no further interrupts allowed – When return from interrupt instruction is executed the contents of the PS are restored from the stack, and the interrupt enable is set to 1 †¢ Special Interrupt line p p – Special interrupt request line for which the interrupt handling circuit responds only t th l di h dli i it d l to the leading edge of d f the signal – Edge –triggered g gg – Processor receives only one request regardless of how long the line is activated – N separate i t No t interrupt di bli t disabling i t instructions tiThe sequence of events involved in handling an interrupt request from a single device. Assuming that interrupts are enabled, the following is a typical scenario: 1. 1 The device raises an interrupt request request. 2. The processor interrupts the program currently being executed. t d 3. Interrupts are disabled by changing the control bits in the PS (except in the case of edge-tri ggered interrupts) interrupts). 4. The device is informed that its request has been recognized, and in response, it deactivates the interrupti d di d ti t th i t t request signal. . The action requested by the interrupt is performed by the interrupt-service routine. 6. Interrupts are enabled and execution of the interrupted program is resumed. Handling Multiple Devices †¢ Multiple devices can initiate interrupts p p †¢ They uses the common interrupt request line y p q †¢ Techniques are q – Polling – Vectored Interrupts p – Interrupt Nesting – Daisy Chaining y g Polling Scheme †¢ The IRQ (interrupt request) bit in the status register is set when a device is requesting an interrupt. The Interrupt service routine polls the I/O devices connected to the bus. †¢ The first device encountered with the IRQ bit set is serviced and the subroutine is invoked. †¢ Easy to implement, but too much time spent on checking the IRQ bits of all d evices, though some devices may not be requesting service. Vectored Interrupts †¢ Device requesting an interrupt identifies itself directly to the processor †¢ The device sends a special code to the processor over the bus. The code contains the – identification of the device device, – starting address for the ISR, – address of the branch to the ISR †¢ PC finds the ISR address from the code. †¢ To add flexibility for multiple devices – corresponding ISR is executed by the processor using a branch address to the appropriate routine – device specified Interrupt Vector. An interrupt vector is the memory address of an interrupt handler, or an index into an array called an interrupt vector table or dispatch table – a table of interrupt vectors (pointers to routines that handle interrupts).Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a context switch, and begins execution of the interrupt handler at the interrupt b i ti f th i t t h dl t th i t t vector. The Interrupt Descriptor Table ( p p (IDT) is specific to the ) p I386 architecture. It tells where the Interrupt Service Routines (ISR) are located. Each interrupt number is reserved for a specific purpose. For example, 16 of the vectors are reserved for the 16 IRQ lines.Q On PCs, the interrupt vector table (IVT or IDT) consists of 256 4-byte pointers – the first 32 (0-31 or 00-1F) of which are reserved f for processor exceptions; the rest f for hardware interrupts, software interrupts. This resides in the first 1 K of addressable memory. Interrupt Nesting †¢ Pre-Emption of low priority Interrupt by another high Pre Emption priority interrupt is known as Interrupt nesting. †¢ Di bli Disabling I t Interrupts d i t during th execution of th ISR the ti f the may not favor devices which need immediate attention. Need a priority of IRQ de vices and accepting IRQ from a high priority device. †¢ The priority level of the processor can be changed y y dynamically. †¢ The privileged instruction write in the PS (processor status word) that encodes the processors priority word), priority. Interrupt Nesting (contd. ) Pro ocessor INTR1 Device 1 INTA 1 Device 2 INTRp .. . Device p INTA p Priority arbitration circuit †¢ Organizing I/O devices in a prioritized structure. g g / p †¢ Each of the interrupt-request lines is assigned a different priority level level. †¢ The processor is interrupted only by a high priority device. Daisy Chaining †¢ †¢ †¢ †¢ The interrupt request line INTR is common to all the devices The interrupt acknowledgement line INTA is connected to devices in a DAISY CHAIN way INTA propagates serially through the devices Device that is electrically closest to the processor gets high hi h priority i i Low priority device may have a danger of STARVATION INTR P Processo r r Device D i 1 INTA Device D i 2 .. Device n D i Daisy Chaining with Priority Group †¢ †¢ Combining Daisy chaining and Interrupt nesting to form p priority group yg p Each group has different priority levels and within each group devices are connected in daisy chain wayINTR1 Proc cessor Device 1 Device 1 INTA 1 INTR p . . . . Device D i 1 INTA p Priority arbitration circuit Device D i 1 Arrangement of priority groups Direct Memory Access (DMA) †¢ For I/O transfer, Processor determines the status of I/O devices, by – – Polling Waiting for Interrupt signal †¢ Considerable overhead is incurred in above I/O transfer processing †¢ To transfer large blocks of data at high Speed, between EXTERNAL devices & Main Memory, DMA approach is often used †¢ DMA controller allows data transfer directly between I/O device d i and d Memory, M with i h minimal i l intervention i i of f processor. Direct Memory Access (DMA) †¢ DMA controller acts as a P rocessor, but it is controlled by CPU †¢ To initiate transfer of a block of words, the processor sends the following data to controller – The starting address of the memory block – The word count h d – Control to specify the mode of transfer such as read or write – A control to start the DMA transfer †¢ DMA controller performs the requested I/O operation and sends a interrupt to the processor upon completion 1 Status and Control Starting address Word count In ? ? ? IRQ 30 IE 1 R/W 0 Done DMA interface g g First register stores the starting address Second register stores Word count Third register contains status and control flags Bits and Flags R/W Done IRQ IE 1 READ Data transfer finishes Interrupt request Raise interrupt (enable) after Data Transfer 0 WRITE Processor Main memory Disk/DMA controller DMA controller Printer Keyboard Disk Disk Network Interface Use of DMA Controller in a computer system Memory accesses by the processor and DMA Cont roller are interwoven †¢ DMA devices have higher priority then processor over BUS control †¢ Cycle Stealing:- DMA Controller â€Å"steals† memory cycles from processor, though processor originates most memory access. †¢ Block or Burst mode:- The of data without interruption †¢ Conflicts in DMA: – Processor and DMA, – Two DMA controllers, try to use the Bus at the same time to access the main memory DMA controller may given exclusive access to the main memory to transfer a blockDMA and Interrupt Breakpoints During D i an I t Instruction Cycle ti C l Bus Arbitration †¢ Bus master: device that initiates data transfers on the bus. †¢ The next device can take control of the bus after the current master relinquishes control †¢ Bus Arbitration: process by which the next device to become master is selected †¢ Centralized and Distributed Arbitration BBSY P Processor r BR BG1 DMA controller 1 BG2 DMA controller 2 A simple arrangemen t for bus arbitration using a daisy chain BR (bus request ) line – open drain line – the signal on this line is a logical OR of the bus request from all the g q DMA devices – BG (bus grant) line – processor activates this line indicating (acknowledging) to all the DMA devices (connected in daisy chain fashion) that the BUS may be used when its free free. – BBSY (bus busy) line – open collector line – the current bus master i di b indicates d i devices that i i currently using h it is l i the bus by signaling this line BBSY Processor BR BG1 DMA controller 1 BG2DMA controller 2 Sequence of signals during data transfer of bus mastership †¢ Centralized Arbitration – Separate unit (bus arbitration circuitry) connected to the bus – Processor is normally the bus master, unless it grants bus mastership to DMA For the timing/control, in previous slide: DMA controller 2 requests and acquires bus mastership and later releases the bus. During its tenure as the bus master, it may perform one or more data transfer operations, depending on whether it is p , p g operating in the cycle stealing or block mode.After it releases the bus, the processor resumes bus mastership. †¢ Distributed Arbitration – All devices waiting to use the bus has to carry out the arbitration process – no central arbiter – Each device on the bus is assigned with a identification number 4-bit – One or more devices request the bus by asserting q y g the start-arbitration signal and place their identification number on the four open collector lines – ARB0 through ARB3 are the four open collector lines – One among the four is selected using the code on the lines and one with the highest ID numberA distributed arbitration scheme Assume that two devices, A and B, having ID numbers 5 and 6, respectively, are requesting the use of the bus. Device A transmits the pattern 0101, and device B transmit s the pattern 0110. p The code seen by both devices is 0111. Each device compares the pattern on the arbitration lines to its own ID, starting from the most significant bit. If it detects a difference at any bit position, it disables its drivers at that bit position and for all lower-order bits. It does so by placing a 0 at the input of these drivers drivers.In the case of our example, device A detects a difference on line ARB I. Hence, it disables its drivers on diff li I H i di bl i d i lines ARB 1 and ARBO. This causes the pattern on the arbitration lines to change to 0110, which means that B has won the contention. Universal Serial Bus (USB) The USB supports two speeds of operation called lowoperation, low speed (1. 5 megabits/s) and full-speed (12 megabits/s). The Th most recent revision of the bus specification (USB i i f h b ifi i 2. 0) introduced a third speed of operation, called high-speed (480 megabits/s).The USB has been designed to meet several key objectives: -P Provid e a simple, low-cost, and easy to use interconnection id i l l t d t i t ti system that overcomes the difficulties due to the limited number of I/O ports available on a computer – Accommodate a wide range of data transfer characteristics for I/O devices, including telephone and Internet connections / , g p – Enhance user convenience through a †plug-and-play† mode of operation USB Bandwidths: A low-speed rate of 1. 5 Mbit/s (~183 kB/s) is defined by USB 1. 0.It is intended primarily to save cost in lowbandwidth human interface devices (HID) such as keyboards, ( ) y , mice, and joysticks. The full-speed rate of 12 Mbit/s (~1. 43 MB/s) is the full speed ( 1. 43 basic USB data rate defined by USB 1. 1. All USB hubs support full-bandwidth. A high-speed (USB 2. 0) rate of 480 Mbit/s (~57 MB/s) was introduced in 2001. All hi-speed devices are capable of falling back to full bandwidth operation if necessary; they are full-bandwidth backward compatible. Connectors a re identical. SuperSpeed ( d (USB 3. 0) rate produces upto 4800 Mbit/s ) d bi / (~572 MB/s or 5 Gbps)Each node of the tree has a device called a hub, which acts as an intermediate control point between the host and the I/0 devices devices. At the root of the tree, a root hub connects the entire tree to the host computer. The leaves of the tree are the I/0 p / devices being served. The tree structure enables many devices to be connected while using only simple point-topoint serial links. Each hub has a number of ports where devices may be connected, including other hubs. In normal operation, a hub g copies a message that it receives from its upstream connection to all its downstream ports.As A a result, a message sent b the host computer is lt t by th h t t i broadcast to all I/O devices, but only the addressed device will respond to that message. A message from an I/O device is sent only upstream towards the root of the tree and is not seen by other devices. Hence, th USB enables th h t t communicate with the I/O H the bl the host to i t ith th devices, but it does not enable these devices to communicate with each other. The USB operates strictly on the basis of polling. A device may send a message only in response to a poll message from the host host.Hence, upstream messages do not encounter conflicts or interfere with each other, as no two devices can send other messages at the same time. This restriction allows hubs to be simple, low-cost devices. USB protocol requires that a message transmitted on a highspeed link is always transmitted p y at high speed, even when the ultimate receiver is a low-speed device. device Hence, a message intended for device D is sent at high speed from the root hub to hub A, then A forwarded at low speed to device D. The latter transfer will take a long time, during which highl ti d i hi h hi h speed traffic to other nodes is allowed to continue.Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit ad dress. This address is local to the USB tree and is not related in any way to the addresses used on the processor bus. A hub may have any number of devices or other hubs connected to it, and addresses are assigned arbitrarily. When a device is first connected to a hub, or when it is powered on, it has the address 0. The hardware of the hub to which this device is connected is capable of detecting that the device has been connected, and it records this f d hi fact as part of i own status i f f its information. Periodically, the host polls each hub to collect status information and learn about new devices that may have been added or disconnected. When the host is informed that a new device has been connected, connected it uses a sequence of commands to send a reset signal on the corresponding hub port, read information from the device about its capabilities, send configuration information to the device, and assign the device a unique USB address. O d i d i th d i i dd Once this thi se quence is completed the device begins normal operation and responds only to the new address. Read about USB protocols Isochronous traffic on USB and USB FRAME

Sustainability Resources And The Future - 1384 Words

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The Stonewall Riots And Women s Rights Movement Essay

Although most people who know about the Stonewall Riots see the riots as the â€Å"birthday of the Gay Liberation Movement,† it perhaps would be more accurate to say that it signified the merging of the Civil Rights or Black Power movement, and Women’s Rights movement, and the political and social unrest amongst gay, lesbian, and transgender and gender variant individuals that would soon become a movement. Incited by a Black trans woman, Marsha P. Johnson, and a Puerto Rican trans woman Sylvia Rivera, the Stonewall Riots are a symbol to this day of some of the most marginalized people in society (ostracized even by the whitewashed, male-dominated Gay Liberation movement) pushing back against racism, sexism, transphobia, fascism, and police brutality and resisting cooptation from white media. However, this would not have been possible without 20th century trailblazers of Gay and Lesbian rights and visibility. According to Richard B. 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